0
\$\begingroup\$

Is there any difference between nonblocking and blocking assignment for the following counters?

module nonblocking_counter ( input clk, input rstn, output reg[3:0] out ); always @ (posedge clk) begin if (! rstn) out <= 0; else out <= out + 1; end endmodule module blocking_counter ( input clk, input rstn, output reg[3:0] out ); always @ (posedge clk) begin if (! rstn) out = 0; else out = out + 1; end endmodule 
\$\endgroup\$
2
  • \$\begingroup\$ Possible duplicate of Difference between blocking and nonblocking assignment Verilog \$\endgroup\$ Commented Oct 15, 2018 at 3:52
  • \$\begingroup\$ Actually, it is not. I understand the difference between them. I think in case of counter the behaviours are equal, am I right? \$\endgroup\$ Commented Oct 15, 2018 at 6:05

1 Answer 1

1
\$\begingroup\$

The circuit generated by synthesis tools will be identical for this code. However in simulation, you have a race condition on the output that feeds the input of another synchronized process when using blocking assignments.

\$\endgroup\$

Start asking to get answers

Find the answer to your question by asking.

Ask question

Explore related questions

See similar questions with these tags.