Verilog: Break an always block

Question

Can I "break" an always blocks in Verilog? I would like to rewrite

 always @(posedge clk_i or posedge rst_i) begin if(rst_i) begin // Do stuff end else begin // Do stuff end end

as follows (which I find cleaner):

 always @(posedge clk_i or posedge rst_i) begin if(rst_i) begin // Do stuff break; end // Do stuff end

This seems dangerously close to forgetting that the operations described are not executed sequentially as in a software programming language, but rather in parallel. — Chris Stratton
– Chris Stratton, Commented Nov 29, 2012 at 15:31

lvd · Accepted Answer · 2012-11-29 14:01:37Z

5

Yes, you should name your begin-end block and then use disable statement like this:

always @(posedge clk_i or posedge rst_i) begin : block_to_disable if(rst_i) begin // Do stuff disable block_to_disable; end // Do stuff end

Though, this is probably non-synthesizable, so you can do such tricks only in simulation (testbenches, etc.).

answered Nov 29, 2012 at 14:01

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