Verilog always block -- testing which posedge occurred

Question

I'm trying to understand an always block construct that I'm seeing a lot. This is all in the context of trying to synthesize some hardware in an FPGA, not simulation.

Sample code:

reg out; always @(posedge clk or posedge reset) begin if (reset) out <= 0; else out <= in; end

What if this block is triggered by a posedge on reset? In that case, we're saying that, by definition, reset is changing. How can we then test the value of reset? It would seem to me that the value of reset should be undefined at the time of it's rising edge. For example, how can we be sure that setup and hold times are observed?

Anyway, I was thinking that might be it -- some sort of idiosyncrasy of Verilog. Clearly, Verilog is not keying on the actual variable names “clk” and “reset”, so that implies some sort of caveat along the lines of: When you test the value of a variable that appears with posedge or negedge in the sensitivity list, then you are testing the value after the edge has occurred. This is in contrast to how other variables are used. For instance, in my example, the variable “in” is likely coming from another D flip-flop that is also triggered by clk, and therefore also changing near the clock ed — Jim M
– Jim M, Commented Aug 29, 2022 at 23:14
This area is only for answers to the question. If you want to clarify the question you are asking, you can edit your question post. — The Photon
– The Photon, Commented Aug 30, 2022 at 2:03
@JimM Answers are for answering questions, use comments to talk to users — Voltage Spike
– Voltage Spike ♦, Commented Aug 30, 2022 at 2:04
I see. But in converting my answer to a comment, the second half of what I said was cut off. So I'll try to add that part below. — Jim M
– Jim M, Commented Aug 30, 2022 at 3:10
@JimM - Re: "how do I add a line break, i.e. a newline, in a comment?" You can't officially do that (a workaround exists, but anyone doing so will have it reverted and told not to bypass that limitation). This and other limitations are intentional. Comments are not for long discussion, just for a few specific purposes, so limits are imposed. More details in the commenting policy. If you have additional questions about how the site works, please ask on Electrical Engineering Meta, not here. Thanks. — SamGibson
– SamGibson ♦, Commented Aug 30, 2022 at 5:24

devnull · Accepted Answer · 2022-08-29 21:12:01Z

I agree it is ugly, but it is the "Verilog way" to implement an asynchronous reset.

How can we then test the value of reset? It would seem to me that the value of reset should be undefined at the time of it's rising edge.

You don't. Don't think like if HDLs were programming languages. The synthesizer looks at this code and concludes: "Hey, this is a rising edge D-flip-flop with an asynchronous reset, active high, always enabled". Then, it gives you one.

in the context of trying to synthesize some hardware in an FPGA

It will just find the best way to implement the described behavior with the available hardware blocks (Vivado/Zynq example):

how can we be sure that setup and hold times are observed?

This is above the scope of Verilog/VHDL. Check the synthesis tool documentation to see how this can be done with constraints and timing simulations.

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