How is saturation defined for a bipolar transistor?

It's singular to me that two primary scientific papers a directly addressing your question have so far been neglected and yet are well-known and widely cited in the literature:

1. A. E. Anderson, "Transistors in switching circuits," Proceedings of the I.R.E., vol. 40, no. 11, pp. 1541-1548; November, 1952.
2. J. J. Ebers and J. L. Moll, "Large-Signal Behavior of Junction Transistors," Proceedings of the I.R.E., vol. 42, no. 12, pp. 1761–1772, Dec. 1954.

Ebers & Moll reference the earlier Anderson paper:

These regions have been defined by Anderson as follows:

Region I: collector current cutoff or collector voltage saturation, Region II: active region, and Region III: collector current saturation, or collector voltage cutoff. 

In the analysis to follow, the dc behavior will again be divided into these three regions. The descriptions of the regions of operation as given by Anderson can be applied to junction transistors as well as to point contact transistors.

(Notes: (1) Anderson had been publishing for some time before, including a 1948 paper I also considered important: "Negative Resistance Chacteristics and Uses of Crystal Diodes". (2) A BJT isn't the only bipolar transistor. The point-contact is another bipolar.)

There's a drawing included on the same page:

(I've added the red underline.)

Anderson's 1952 paper includes a specific circuit used to elucidate the three regions he discusses in Figure 3, including a resulting chart:

(It does take external circuits to perform the necessary experiments needed to make observations and arrive at experimental results.)

I'd like to strongly suggest reading the above two papers.

I've also written here more than a few times on the topic. Including this one on the topic of bipolar saturation in the context of the 1954 version of the Ebers-Moll model for bipolars. It's not as though the topic hasn't come up before.

That said, I obviously can't speak to your exam. I haven't your textbooks, handouts, nor have I attended your lectures. So if you are asking about what you should say in order to get good marks, that's on you.

But I can say, with respect to the scientific literature on the topic, that saturation in bipolars means the collector-base junction is forward biased.

Please refer to my link for more details, including not only the ability to quantiatively predict saturation behavior (and not just make hand-waving guesses about it) but also the ability to predict the unique and unusual case where the collector current can actually reverse direction in saturation. (Something I cannot recall having seen a mention of, on this site, outside of my own writing.)

It's my hope that the above references to the key scientific papers on the topic will satisfy those around you on the topic. At the very least, you can make reference and hope they will see it favorably.

Based on your comments this is an exam question and since there is a load line, it means that the transistor is in some circuit instead of examined alone.

The circuit would likely consist of load resistor on collector to 10V, which appears to be 100 ohms in your plots based on the load line, and then some biasing circuit and possiby a small signal AC input on the base, which cannot be determined, but it will define the base current.

Basically the curves tell what is the expected collector current or rather the collector voltage based on input base current.

In such case the saturation region is usually defined to be the left part which cannot be reached by inputing the base current withing limits of the circuit. But as the circuit is unknown, we don't know what is the valid base current range, if some extrapolation or interpolation is needed for the base current curves.

However, there will always be a point after which increasing base current has little to no effect. As an example, in the datasheet you link to, the table on first page tells saturation voltages, and they are measured in a condition where ratio of collector and base current is 20, so the current gain has dropped a lot from the nominal 110 to 800 range.

There is also curves in Figure 6 which defines Vbe and Vce in saturation, in a condition where current gain has dropped down to 10.

So without further knowledge on the exam assignment and what has been talked in the lectures, the whole area left from the topmost 400uA Ib curve and load line would be the saturation region which cannot be reached. More precisely, if the circuit allows only Ib up to 300uA then that should be used as the limit.

Textbooks also define the saturation operation of the transistor alone without any specific circuit where Vc is below Vb.

There are several ways saturation can be defined, depending upon circumstances.

OP is looking at a graph of transistor characteristics. On this graph saturation corresponds to operation along the dashed line. (It is not possible to operate to the left of the dashed line).

The physics definition has both emitter-base and collector-base junctions forward biased.

In piece-wise linear analysis, the characteristics are approximated by straight lines. In saturation IC < B*IB and VCE = VCEsat which is usually taken as about 0.2 V.

I am confused by your question, because there is no combination of \$I_C\$ and \$I_B\$ that can result from any of the values of \$V_{CE}\$ represented by your solid red line. There is no scenario in which \$V_{CE}\$ lies to the left of your dotted red line, regardless of \$I_B\$ or \$I_C\$. The best I am able to do here is explain the meaning of that graph, and how it is produced, which may help if you have misinterpreted it somehow.

If we assumed that \$V_{BE}=0.7{\rm V}\$, and for the sake of argument we claim that saturation occurs when \$V_{CE}<V_{BE}\$, this condition would be represented on the graph by the region to the left of \$V_{CE} = 0.7{\rm V}\$. In reality, though, this "threshold", or "knee" value shifts rightwards as \$I_B\$ is raised, partially due to this 0.7V being only an estimate. It changes with \$I_B\$, a trend clearly visible in the graph. You would expect it to vary with \$I_B\$, because the base-emitter junction is an imperfect silicon diode, whose forward voltage increases somewhat with increasing \$I_B\$.

You might interpret any single line on that graph, for any fixed \$I_B\$, as follows: the horizontal section represents a state in which the transistor is perfectly able to achieve collector current \$I_C = \beta I_B\$. In other words, \$V_{CE}\$ is not so small as to prevent this "ceiling" being reached. This is the region where you can actually trust the transistor to behave according to \$I_C = \beta I_B\$, and therefore this is the active region. The condition prevailing in this region is \$V_{CE} > V_{BE}\$, to the right of the knee. In this flat section, it may look like the transistor has reached some limit, and is no longer amplifying, but in fact this is where \$I_C = \beta I_B\$.

If you were to explicitly apply \$V_{CE}\$ that falls to the left of the knee on that line, there's no longer sufficient potential difference to reach that ceiling of collector current. In other words, you no longer have \$I_C = \beta I_B\$ - instead you have \$I_C < \beta I_B\$. That's assuming \$\beta\$ is constant - it isn't, which is another consideration, but we'll have to ignore that little complication here.

Note also that it's necessary for \$V_{CE}\$ to be significantly lower than \$V_{BE}\$ to forward bias the collector-base junction, to the point where you begin to see a fall away from \$I_C=\beta I_B\$ behaviour.

I deliberately said "if you explicitly apply \$V_{CE}\$" with good reason - it is exactly how this graph is produced, by applying that potential difference \$V_{CE}\$ using a voltage source:

^{simulate this circuit – Schematic created using CircuitLab}

Simulating a sweep of source \$V_{CE}\$, for several values of fixed \$I_B\$ gives me this familiar picture:

The above is forcing \$V_{CE}\$ to some value, and for the condition \$V_{CE} < V_{BE}\$ the transistor is unable to comply with \$I_C = \beta I_B\$, a state we call saturation.

The above scenario is very different from a typical common-emitter setup, with collector resistor, in which we allow the transistor to choose its own \$V_{CE}\$ as a function of \$I_B\$. This is not a graph of dependent \$V_{CE}\$ vs. independent (known and controlled) \$I_B\$; this is a graph where we measure dependent \$I_C\$ as a result of a \$V_{CE}\$ that we set explicitly.

I don't understand what's confused you, exactly, but this graph is agreeing with the claim that a transistor is saturated when it is unable to perform \$I_C=\beta I_B\$, and this happens when \$V_{CE}<V_{BE}\$.