Questions tagged [intel-fpga]

Question 1

I’m trying to test the LVDS output on my Altera DE2-115 board using Quartus Prime 18.1 Lite. My goal is just to generate and output a clock signal over an LVDS pair using the ALTLVDS_TX Megafunction. ...

Question 2

I’m trying to generate a clock for an external ADC using a Cyclone IV E (EP4CE115F2907N) on a Terasic DE2-115 board. I connected the PLL output to pin M25, which I configured as LVDS in Quartus. ...

Question 3

I’m a complete beginner in FPGA and HDL design, and I’m starting a small project to control a 4-floor elevator using a finite state machine (FSM). My ultimate goals are: 1. Derive the equivalent logic ...

Question 4

I am trying to connect two MACs in GMII mode - using a SoC to connect them, and routing GMII signals through the Fabric. In the spec for the Intel MAC GMII IP, it assumes connection to PHY. This IP ...

Question 5

I have precompiled (with db and incremental_db folders, so it have sof/pof files) Quartus Prime (22.1std.1 Build 917 02/14/2023 SC Lite Edition) project and want to open "Technology Map Viewer (...

Question 6

I am in the process of learning about communication between SDRAM and OCM via DMA, using the Agilex-5. The idea will be to write 0xdeafbeef to the SDRAM, then ...

Question 7

I have managed to implement the internal oscillator in the CPLD MAX II: EPM240T100C5. From what I can see it can be set to either I have used the wizard to generate the code for 5.56 MHz. The files ...

Question 8

I want to do synthesizable always block, that would execute code by d1 signal changing (posedge and ...

Question 9

I'm using a CycloneIV E, and would like to have both JTAG and AS flash programming options available. Do I need two headers, like Figure 8-28 suggests, or can these be combined, as the pins used for ...

Question 10

What would be the easiest way to create a reset signal after new configuration has been downloaded to an FPGA? I've always done a reset manually via a switch .. but there has to be a better way - ...

Question 11

I am using an Altera Cyclone V FPGA (5CGXFC7D6F27I7N) on a custom carrier board to convert DisplayPort video (input) to BT.656 video data (output). The output video data is then sent to an encoder, ...

Question 12

I have this diagram from my class of how 3 6-input LUTs are used to create a Full 4-bit adder. It's not particularly clear, but each 6-input LUT has 2 outputs (so I suppose they're really operating as ...

Question 13

I am working on a school project to build a 'weather station' out of a DE2-115 FPGA board and after covering almost everything, the project will not work with I2C. I am using a NIOS-II to run the I2C ...

Question 14

We have developed a cyclone 10 Lp FPGA (10cl016Y) board, the Schematic is shown below The FPGA chip configures good through JTAG using .sof file, but if the Flash chip is programmed using .jic file, ...

Question 15

How to decrease system clock frequency in Quartus II from standard 50 MHz to 2 Hz (two clock fronts per second)? I find out it easier using constraints editing way, namely, SDC (Synopsys Design ...

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Questions tagged [intel-fpga]

How to test LVDS output clock on DE2-115 using ALTLVDS_TX Megafunction?

Generating LVDS clock on Cyclone IV E (M25/M26 pins)

What’s the recommended workflow to implement an FSM in Verilog and generate waveforms in Intel Quartus? (Beginner question)

Ethernet GMII MAC to MAC Loopback

How to open the precompiled Quartus Prime project

SDRAM to OCM via DMA on the Agilex 5

Quartus internal oscillator

Reaction on signal changing using always block in Verilog not work after FPGA programming

Can I combine AS and JTAG headers for CycloneIV?

FPGA Reset Circuit after Download

FPGA Cyclone V GX Fails at Low Temperatures (-40C)

How would a 4-bit full-adder be implemented in a Cyclone V FPGA?

I2C Timeout Error on DE2-115 Board with ADS1115

Cyclone 10lp FPGA not configuring through Flash chip (EPCQ64A ), but configures ok through JTAG (.sof)

Decrease system clock frequency in Quartus II?

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