Questions tagged [system-verilog]
In the semiconductor and electronic design industry, SystemVerilog is a combined hardware description language and hardware verification language based on extensions to Verilog.
548 questions
0 votes
1 answer
78 views
Use of new constructor in extended classes from uvm base classes
Code link: [https://edaplayground.com/x/9cte] For the below code ...
- 177
3 votes
2 answers
142 views
JK flip flop behavior on startup in Verilog
I've tried to implement a JK flip flop in Verilog, but while testing, I found that whatever inputs of j and k I give on startup, until I reset the flip flop (j=0, k=1), the outputs will not be seen ...
- 31
1 vote
1 answer
90 views
Why is the waveform not matching? (2 clock delay in FSM code)
Context : I have been tasked with testing a HC-04 Ultrasonic sensor with Verilog, and below is the Verilog code, the testbench and the waveform that I am getting, ...
- 169
1 vote
1 answer
122 views
Different outputs for RTL and gate level netlist simulations for a latch used in clock gating
I am trying to implement clock gating logic manually using a latch and an AND gate as shown in the figure. The latch has an enable (en) and a done signal which are ...
- 19
2 votes
1 answer
75 views
1 vote
1 answer
120 views
What to do when a Verilog state machine simulation doesn't reflect the signals?
I'm working on a Verilog project using ModelSim, and I've created a testbench to simulate the behavior of a module called Elevator_FSM, which models an elevator's operation. My goal is to assign ...
- 61
2 votes
1 answer
125 views
Analyzing unexpected output from Verilog bit unpacking and reassembly logic
I'm working on a Verilog task that rearranges bits from a 312-bit word into a new 312-bit format using 8-bit temporary storage (temp[39]). Below is a simplified ...
- 673
-1 votes
1 answer
83 views
1 vote
1 answer
72 views
How blocking assignment affect non-blocking assignment in Verilog?
module t; reg a; initial a <= #4 0; initial a <= #4 1; initial $monitor ($time,,"a = %b", a); endmodule Output of above Verilog code is: ...
- 193
3 votes
2 answers
440 views
Why is Vivado connecting this reset to the CE pin when the R pin is available?
Vivado is connecting up the reset signal through a LUT to the CE pin of the FDRE, even though the R pin is available. This is a 2k signal, and it's using up 2k LUTs to do this, unnecessarily. Any ...
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0 votes
0 answers
55 views
Vivado Simulation Bug for 4 bit asynchronous ripple counter
I am currently learning Verilog and tried to build an asynchronous counter using T flip flops. But, during the simulation, my most significant three bits become one without any clock signal from the ...
1 vote
1 answer
129 views
SystemVerilog's $fdisplay/$fopen don't create a file
I am trying to save the results of simulation to a file from a testbench. Here is the problematic snippet: ...
1 vote
1 answer
66 views
Clocking block skew in interface modport
For the code: EDA Playground In the interface code: ...
- 177
2 votes
1 answer
122 views
How can I make sure the signal is not X when accessed?
I just found a bug in hardware that wasted hours of my time, and I never thought about it. I have something like that: ...
- 450
1 vote
1 answer
158 views
Bad handle reference while calling a task in SystemVerilog
I am trying to create the basic testbench for a simple single port memory but getting the following error: ...
- 177