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How does the Cortex M0+ processor use the AHB-Lite interface to fetch instructions and data? Are instruction fetches done always using NONSEQ? How does it fetch data from memory (using burst or NONSEQ transfers)?

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From the ARM M0+ manual, revision r0p1:

AHB-Lite interface
Transactions on the AHB-Lite interface are always marked as non-sequential.

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