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I am writing Verilog code for a 4-bit BCD adder. I am having trouble writing the top module and understanding how to call the other modules into the top module. Here are my codes.

module topmodule(x, y, cin, cout, hex0, hex1, hex2, hex3, hex4, hex5, L5, fulladder, ssdxconverter, ssdyconverter, sumconverter); input [3:0] x; input [3:0] y; input cin; output cout; output [13:0] hex0; output [13:0] hex2; output [13:0] hex4; wire ///4-bit adder/////////////////////////////////////////////////////////////////////////// module L5(cin, x, y, sum, cout); input [3:0] x; input [3:0] y; input cin; output cout; output [3:0] sum; wire [3:1] carryout;// since carryout starts with 1 ends wtih 2 (total 3) for this 4 bit adder fulladder(cin, x[0], y[0], sum[0], carryout[1]);// need cin, x0,y0, to produce cout1 and sum0 fulladder(carryout[1], x[1], y[1], sum[1], carryout[2]);// need cout1, x1,y1, to produce cout2 and sum1 fulladder(carryout[2], x[2], y[2], sum[2], carryout[3]);// need cout2, x2,y2, to produce cout3 and sum2 fulladder(carryout[3], x[3], y[3], sum[3], cout);// need cout3, x3,y3, to produce cout and sum3 endmodule //singlebit adder////////////////////////////////////////////////////////////////////////////////////////// module fulladder(x, y, cin, sum, cout); // declaring the name of this project FA(full adder) and all the elements within the code input x, y, cin;// inputs are a, b, and cin output sum, cout;// outputs are sum and cout wire w0, w1, w2;// using wire to connect input and output with some other element in the circuit xor u0(w0,x,y); xor u1(sum,w0,cin); and u2(w1,cin,w0); and u3(w2,x,y); or u4(cout,w1,w2); // we are adding gate names before the bracketA endmodule //x converter////////////////////////////////////////////////////////////////// module ssdxconverter(x, hex0); input [3:0] x; input [3:0] y; output reg [13:0] hex0; always @(x) begin case(x) 4'b0000:hex0 = 14'b1111111_1000000;//0 4'b0001:hex0 = 14'b1111111_1111001;//1 4'b0010:hex0 = 14'b1111111_0100100;//2 4'b0011:hex0 = 14'b1111111_0110000;//3 4'b0100:hex0 = 14'b1111111_0011001;//4 4'b0101:hex0 = 14'b1111111_0010010;//5 4'b0110:hex0 = 14'b1111111_0000010;//6 4'b0111:hex0 = 14'b1111111_1111000;//7 4'b1000:hex0 = 14'b1111111_0000000;//8 4'b1001:hex0 = 14'b1111111_0010000;//9 4'b1010:hex0 = 14'b1111001_1000000;//10 4'b1011:hex0 = 14'b1111001_1111001;//11 4'b1100:hex0 = 14'b1111001_0100100;//12 4'b1101:hex0 = 14'b1111001_0110000;//13 4'b1110:hex0 = 14'b1111001_0011001;//14 4'b1111:hex0 = 14'b1111001_0010010;//15 endcase end endmodule ///y converter module ssdyconverter(y,hex2); input [3:0] y; output reg [13:0] hex2; always @(y) begin case(y) 4'b0000:hex2 = 14'b1111111_1000000;//0 4'b0001:hex2 = 14'b1111111_1111001;//1 4'b0010:hex2 = 14'b1111111_0100100;//2 4'b0011:hex2 = 14'b1111111_0110000;//3 4'b0100:hex2 = 14'b1111111_0011001;//4 4'b0101:hex2 = 14'b1111111_0010010;//5 4'b0110:hex2 = 14'b1111111_0000010;//6 4'b0111:hex2 = 14'b1111111_1111000;//7 4'b1000:hex2 = 14'b1111111_0000000;//8 4'b1001:hex2 = 14'b1111111_0010000;//9 4'b1010:hex2 = 14'b1111001_1000000;//10 4'b1011:hex2 = 14'b1111001_1111001;//11 4'b1100:hex2 = 14'b1111001_0100100;//12 4'b1101:hex2 = 14'b1111001_0110000;//13 4'b1110:hex2 = 14'b1111001_0011001;//14 4'b1111:hex2 = 14'b1111001_0010010;//15 endcase end endmodule ///bcdoutput converter/////////////////////////////////////////////////////////////////////////// module sumconverter(sum, c, hex4); input c; input [3:0]sum; output reg [13:0] hex4; always @(sum) begin if(c==0) case(sum) 4'b0000:hex4 = 14'b1111111_1000000;//0 4'b0001:hex4 = 14'b1111111_1111001;//1 4'b0010:hex4 = 14'b1111111_0100100;//2 4'b0011:hex4 = 14'b1111111_0110000;//3 4'b0100:hex4 = 14'b1111111_0011001;//4 4'b0101:hex4 = 14'b1111111_0010010;//5 4'b0110:hex4 = 14'b1111111_0000010;//6 4'b0111:hex4 = 14'b1111111_1111000;//7 4'b1000:hex4 = 14'b1111111_0000000;//8 4'b1001:hex4 = 14'b1111111_0010000;//9 4'b1010:hex4 = 14'b1111001_1000000;//10 4'b1011:hex4 = 14'b1111001_1111001;//11 4'b1100:hex4 = 14'b1111001_0100100;//12 4'b1101:hex4 = 14'b1111001_0110000;//13 4'b1110:hex4 = 14'b1111001_0011001;//14 4'b1111:hex4 = 14'b1111001_0010010;//15 endcase else if(c==1) begin case(sum) 4'b0000:hex4 = 14'b1111001_0000010;//16//c4 is 1 4'b0001:hex4 = 14'b1111001_1111000;//17 4'b0010:hex4 = 14'b1111001_0000000;//18 4'b0011:hex4 = 14'b1111001_0010000;//19 4'b0100:hex4 = 14'b0100100_1000000;//20 4'b0101:hex4 = 14'b0100100_1111001;//21 4'b0110:hex4 = 14'b0100100_0100100;//22 4'b0111:hex4 = 14'b0100100_0110000;//23 4'b1000:hex4 = 14'b0100100_0011001;//24 4'b1001:hex4 = 14'b0100100_0010010;//25 4'b1010:hex4 = 14'b0100100_0000010;//26 4'b1011:hex4 = 14'b0100100_1111000;//27 4'b1100:hex4 = 14'b0100100_0000000;//28 4'b1101:hex4 = 14'b0100100_0010000;//29 4'b1110:hex4 = 14'b0110000_1000000;//30 4'b1111:hex4 = 14'b0110000_1111001;//31 endcase end end endmodule ```
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  • \$\begingroup\$ There are many freely available resources for a Verilog beginner. What exactly are you confused about? What have you tried, what did you expect to happen, and what actually happened? \$\endgroup\$ Commented Oct 21, 2020 at 0:19
  • \$\begingroup\$ So I am trying to create a main module to diplay my outputs, but I am confused of how to make the main module. For example, how to call out other modules and decide what variables I need to wire. \$\endgroup\$ Commented Oct 21, 2020 at 0:23
  • \$\begingroup\$ Each time you instantiate a submodule you have to not only say what type of module you are instantiating, but you have to give the instance a unique name. For example fulladder adder_1(...ports...);. \$\endgroup\$ Commented Oct 21, 2020 at 4:42

1 Answer 1

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There are 2 main problems with your code:

  1. You must not try to declare module names as port names
  2. You must specify an instance name for each module instance, as pointed out in a comment on your question

The L5 module has syntax errors on the lines where you place instances of the fulladder module. Here is one way to fix those errors:

module L5(cin, x, y, sum, cout); input [3:0] x; input [3:0] y; input cin; output cout; output [3:0] sum; wire [3:1] carryout;// since carryout starts with 1 ends wtih 2 (total 3) for this 4 bit adder fulladder i0 (cin, x[0], y[0], sum[0], carryout[1]);// need cin, x0,y0, to produce cout1 and sum0 fulladder i1 (carryout[1], x[1], y[1], sum[1], carryout[2]);// need cout1, x1,y1, to produce cout2 and sum1 fulladder i2 (carryout[2], x[2], y[2], sum[2], carryout[3]);// need cout2, x2,y2, to produce cout3 and sum2 fulladder i3 (carryout[3], x[3], y[3], sum[3], cout);// need cout3, x3,y3, to produce cout and sum3 endmodule

A unique instance name is required between the module name and port list. I chose simple names like i0 and i1, but they can be any legal Verilog identifier (like signal names and module names).

For more details, refer to How to instantiate a module.

Follow that pattern for topmodule if you want instances of L5, ssdxconverter, etc. However, you need to fix the syntax errors in the top module port list. Here is one way:

module topmodule ( input [3:0] x, input [3:0] y, input cin, output cout, output [13:0] hex0, output [13:0] hex2, output [13:0] hex4 ); // You need to fill in the module port connections inside the empty parentheses: L5 i0 ( ); ssdxconverter i1 ( ); ssdyconverter i2 ( ); sumconverter i3 ( ); endmodule

I used a simpler style of port list (the ANSI style), where there is no need to duplicate the port names. As you can see, the module names are no longer in the port list; they are placed as instances instead. You need to fill in the empty port connections for each instance.

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