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This is a 4 bit counter code written using Verilog HDL on Quartus. Can somebody explain why is my output o always showing 0?

Code in Text :

module ab(i,o,r); input i,r; output [3:0]o; counter4bit c4(i,o,r); endmodule module counter4bit(clk,y,reset); input clk,reset; output reg [3:0]y; always@(posedge clk, posedge reset) if (clk == 1) y <= y + 1; else if (reset == 1) y <= 0; endmodule

If I write the reset condition first inside the always block it seems to run fine:

if (reset == 1) y <= 0; else if (clk == 1) y <= y+1; )

enter image description here

enter image description here

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    \$\begingroup\$ @toolic I'm sorry I don't know what the "testbench code" is . I'm very new to this Verilog coding actually. \$\endgroup\$ Commented Sep 29, 2021 at 20:45
  • \$\begingroup\$ It's good that you posted your actual code now. I added formatting for the code for you. In the future, you should try to format it yourself. I'm not familiar with Quartus tools; my guess is that it automatically creates a testbench for you so that you can run a simulation to generate those waveforms. \$\endgroup\$ Commented Sep 29, 2021 at 20:48
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    \$\begingroup\$ Thanks for the edit. From next time I will keep these things in mind. \$\endgroup\$ Commented Sep 29, 2021 at 20:58
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    \$\begingroup\$ @AkibAhmed I gather you want a clocked FF with an async reset? If so, you test the asynchronous reset signal first. Then, I think it can be synthesized. Otherwise? Do you know of an FF that checks its clock before an async reset? Maybe someone has built one. But I don't think it can be readily synthesized. (Probably can be simulated, though.) \$\endgroup\$ Commented Sep 29, 2021 at 21:11

1 Answer 1

Reset to default
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From your waveform image, it looks like your reset signal (r) is always 0. Since you are not properly resetting your counter, I would expect the output to be unknown (X) instead of 0. I can't explain why the waves show 0 because I am not familiar with Quartus tools.

However, you should really assign the reset signal to 1 at time 0, then assign it to 0 after a couple clock cycles (say at time 20ns). This should properly reset the counter.

Your always block is not the traditional way to code a counter. You should not check the clock signal inside the block that way. The conventional way is as follows:

always @(posedge clk, posedge reset) begin if (reset == 1) begin y <= 0; end else begin y <= y + 1; end end
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