Current Mirror: Output resistance of stacked MOS used as current source

I am trying to calculate and simulate the output resistance of a stacked NMOS transistor used as current mirror load and I have a few doubts about hand calculation and simulation setup.

1. The circuit to analyse consists of M stacked NMOS transistors as shown in the pic below (the configuration is also known as Poor Man's Cascade from Razavi Textbooks). In principle I am aware that once the proper biasing conditions are set, the upper-stack transistor will be biased in saturation while the remaining M-1 will be biased in linear (triode) mode given that all devices share the same V_TH. In principle, this device should be equivalent to a single NMOS transistor having a channel M-times longer, and therefore, its output resistance is M-times larger than the single devices

My question is in principle how to model the stack-up from a small-signal point of view. Should it be modeled with 5 series resistors (each one for every NMOS transistor biased in triode mode) and the upper-stack transistor using a classical pi model for NMOS. The equivalent circuit would look like a source-degenerated pi model, where the degeneration resistor would be

$$R_{S} = R_1 + R_2 + ... R_{M-1}$$

and the low-frequency output resistance looking into the upper-stack NMOS drain would be:

$$r_{out} = g_{m_M}*r_{out_M}*R_{S}$$

Is this reasoning correct? I have setup the most simple version of this circuit (using only 2 transistors) in a test bench to verify this approach using a DC voltage source to bias the gate of the transistors and a bias-tee (L-C) at the drain of transistor M to provide the required drain VDD. I then connect the bias-tee capacitor to an S-parameter port, from which I can directly evaluate the output resistance (real) looking into the drain of M.

As additional test I read back the transistor parameters from the DC simulation and calculate the output resistance using the equation above. For a given proper bias point where M is in saturation and M-1 is in linear mode I get:

S-parameters result at 10 Hz: output resistance of ~30 Ohms Equation-based result: ~580k ohms

Given that I've had this branch already placed in a bias mirror, I think the equation-based results is closer to reality than the S-parameter one, but I do not yet grasp why.

Any hint where my modelling/thinking is incorrect?

Thanks