Questions tagged [memory]
Consider instead more specific tags, e.g., dram, sram, flash
899 questions
0 votes
0 answers
73 views
Connecting an auxiliary battery to payloader for stereo memory
I have a New Holland W130b loader with a main battery disconnect switch. The switch kills ground to the system. The stereo I removed was analog, I wanted digital with bluetooth and I can not see the ...
1 vote
1 answer
122 views
Shared Pin Mapping for SD Card and NAND Flash Interfaces on MPU
I am using a Microchip SAMA5D27 Wireless System-On-Module 1 (ATSAMA5D27-WLSOM1) MPU SOM Module with a Micron MT29F4G08ABADAWP-IT:D NAND Flash device for storing the boot image. I will also use a 4-bit ...
- 1,953
5 votes
2 answers
875 views
Why does ECC add 1/4 more DRAM ICs with DDR5, rather than 1/8?
While shopping for 32 GiByte DDR5 ECC UDIMMs, I found pictures with 20 identical DRAM ICs, where I was expecting 18, because that's been the usual number for large DDR/DDR2/DDR3/DDR4 ECC UDIMMs, and I ...
- 2,085
1 vote
0 answers
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DDR4 bit, byte, nibble swapping
I’m working on a DDR4 PCB layout and want to confirm the allowed rules for bit swapping, byte lane swapping, and nibble swapping, especially when ECC or CRC is enabled. From what I understand so far: ...
-2 votes
1 answer
136 views
Can I connect this RAM to a breadboard
I'm looking at this RAM: https://gr.mouser.com/ProductDetail/Ramxeed/MB85R4M2TFN-G-JAE2?qs=sGAEpiMZZMs6Aik9Fp479ij4Y1Ujk4wm%252B7sI6f6xMBM%3D How big diameter are the pins of this RAM? Can I stick it ...
1 vote
0 answers
56 views
NOR flash chip memory organization 32Mx8 vs 64Mx4 performance and overall differences
I am in searching of better 256Mbit replacement of existing 128Mbit QSPI NOR flash memory chip on HW platform I work on and have met very interesting feature among the others which is Memory ...
1 vote
1 answer
186 views
DDR3 in a fly-by routing
I recently completed fly-by routing for 2 x DDR3 and a Zynq 7000 chip by studying their app notes or general notes on how to do fly-by routing. Now that I finished the routing then I started having ...
- 359
5 votes
10 answers
1k views
Why is copying data in RAM inherently slow?
When you're programming for performance, it's important to reduce the amount of copies, because copying data is (relatively) slow. But why does it have to be that way? In my naïve conception, data is ...
- 151
2 votes
1 answer
254 views
Issue with QUAD OUTPUT FAST READ (0x6B) on Micron NOR Flash (MT25QL128ABA)
I am using a Micron NOR Flash Chip (MT25QL128ABA) along with a Zynq-7020 FPGA. I have implemented a QSPI driver in Verilog, which successfully communicates with the Flash behavioral Verilog model in ...
1 vote
2 answers
89 views
Spartan-6 MIG DDR3 Write Issue: Incorrect DQS to CK Alignment
I'm implementing a DDR3 controller using Xilinx MIG on a Spartan-6 XC6SLX16-2FTG256 FPGA. The DDR3 memory I'm using is MT41J128M16. The issue is that, during write operations, the upper byte (DQ[15:8])...
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0 votes
3 answers
139 views
In a solution to an exercise, each memory address has a length of 64 bits, and I do not understand why
In a solution to an exercise in my notes for a Computer Architecture course, it is stated that each memory address has a length of 64 bits, and I do not understand why. The problem statement is as ...
- 235
0 votes
2 answers
157 views
Indirect Addressing P16F877
Suppose i have two numbers n1 & n2, one in bank 0 and the other in bank 2, i want to do a sum operation on them using the indirect addressing approach, here is the code from my lecture which is ...
- 555
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How are multiple DDR5 DIMMs wired into to the same channel?
This question is about how multiple DDR5 DIMMs in the same memory channel are wired to the processor. This is mostly an electrical engineering question, and the goal to answer this question: Will re-...
- 2,268
7 votes
4 answers
2k views
How does pipelined CPU access both code and data memory in real life?
In the Digital Design and Computer Architecture RISC-V Edition page 442, a pipelined CPU is designed with separate instruction and data memories, as shown in the figure below. However, this picture ...
- 193
0 votes
2 answers
184 views
How does nMOSFET conduct both ways in a DRAM cell?
How does nMOSFET conduct both ways in a DRAM cell? Doesnt the constrain of always keeping the source lower than the drain in potential restrict current flow only one way? I know a 4 terminal nMOS is ...
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