Questions tagged [xilinx]

Question 1

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Question 2

I'm trying to synthesize the following hardware in Vivado, which contains an array of my_struct_t. To reach timing closure, it's important that this array is ...

Question 3

Both attributes are used to tell Vivado if we want to use the enable pin of a DFF. What's the difference between them? When is one more preferable than the other?

Question 4

In 7 Series FPGAs Configuration (UG470), Xilinx says, DOUT is the data output for a serial configuration daisy-chain. DOUT is clocked out on the falling edge of CCLK. What does it mean by 'clocked ...

Question 5

I'm trying to communicate with a temperature sensor (TMP461) without using the PS, relying solely on the Programmable Logic. For this purpose, I'm using JTAG to AXI bridge and the AXI IIC IP provided ...

Question 6

I’m new to working with the ZCU106 (Zynq Ultrascale+ MPSoC) evaluation board and am trying to write a simple "Hello World" program (e.g., toggling a user LED) using Simulink Embedded Coder ...

Question 7

I am using ZYNQ7010 SoC from Xilinx (AMD) to control two DDR3 memories with fly by routing. I am trying to run simulation to check signal integrity overall. Where can I find risetime information for ...

Question 8

I am a uni student familiar with xilinx products and I have never used trenz electronics but I can't seem to establish a connection through jtag using the trenz electronics te0720 with the te0706 ...

Question 9

I'm implementing a DDR3 controller using Xilinx MIG on a Spartan-6 XC6SLX16-2FTG256 FPGA. The DDR3 memory I'm using is MT41J128M16. The issue is that, during write operations, the upper byte (DQ[15:8])...

Question 10

I am kind of finishing up hardware design based on AMD Zynq 7010 SoC which has different peripherals. This is the most complex design that I have done in my past and I wanted to get some sort of ...

Question 11

Im trying to program my board via the FT232 because I'll be using that chip in my own development board around the same SOM my dev board uses (MYD-C7Z020 V2). My board doesn't show up in HW manager. ...

Question 12

I am using this image sensor and interfacing with FPGA (Zynq 7010). I understand what needs to be terminated on FPGA side and I understand what I/O is supported such as LVCMOS18_F_8_HP, ...

Question 13

I am relatively new to FPGA board design. I am interfacing HDMI TX to FPGA (Zynq 7010 SoC) as shown below. My understanding is that Zynq supports TMDS signals so I can use any of High-Range I/O in PL ...

Question 14

I am referencing an existing design that connects this camera through MIPI CSI-2 interface. I could just take this pinout and have it implemented on my custom board using same SoC used in the ...

Question 15

I'm working with Zynq UltraScale+ and using the XilSKey library for EFUSE programming over JTAG. I came across the JtagReadUltra function, which prepares a buffer (<...

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Questions tagged [xilinx]

What could be wrong with my vivado simulation? The clock isn't alternating

Using LUT RAM for an array of structs in Vivado

What's the difference between 'EXTRACT_ENABLE' and 'DIRECT_ENABLE'?

What does 'clocked out' mean?

Unable to control IIC sensor using JTAG to AXI Master and AXI IIC Xilinx IPCore

Can I program ZCU106 (Zynq Ultrascale+ MPSoC) with Simulink Embedded Coder without Vitis?

Risetime of DDR3 clock signal AMD Xilinx

JTAG Not Working On TE0720/TE0706/TE0790-03

Spartan-6 MIG DDR3 Write Issue: Incorrect DQS to CK Alignment

Zynq SoC Schematic review

Programming Xilinx board using FT232 breakout board

MIPI D-PHY Image sensor with SoC

AMD Zynq SoC with HDMI

Understanding MIPI CSI-2 signals level

Efuse programing using XilSKey lib, Zynq UltraScale+

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