Questions tagged [vlsi]

Question 1

Is there anyone around here that has experience with .yal files used for VLSI? I need some guidance on how to get the graph abstraction from the netlist. For ...

Question 2

I am working on the 4 bit SAR ADC in LTspice, where I was able to finish the sample and hold circuit, comparator circuit and R-2R ladder but the issue is I was unable to move with clock generator and ...

Question 3

As per this circuit shown, gate of M2 is grounded. As Vgs=0, M2 won't conduct current as being an NMOS. If that is the case, how would voltage division occur and how does M2 forms a source ...

Question 4

When we draw the cross-sectional view of the below given circuit using NWELL CMOS Fabrication technique, should we use a single shared NWELL or separate NWELLS for each of the PMOS? If separate, then ...

Question 5

I developed this code for a Graph convolutional network (GCN) module in system verilog: ...

Question 6

It seems straightforward to count the transistors on a chip, but it's not. For instance, many logic gates use transistors in parallel to increase the drive current. Are these transistors counted as ...

Question 7

I have the following circuit for which I need the critical path: For Path 1: This has the maximum number of stages Logical effort (NAND3) = 5/3. Total parasitic effort for this stage (excluding ...

Question 8

I am trying to design an LC VCO in TSMC's 65nm CMOS process. First I designed an LC oscillator without any tuning i.e. I used MIM capacitors which are included with the PDK as well as inductors from ...

Question 9

I have recently started designing analog ICs as part of my academic work. So far all I do is take topologies given in textbooks or papers and try to design them in the PDKs available at my university. ...

Question 10

I've been looking around for discrete, specific, and practical answers to the question "how many inputs can a (N)AND/(N)OR gate have?" as it relates to ASIC/VLSI/MOSFET/semiconductor ...

Question 11

I have some experience in OTA design for both 180 nm and 130 nm technologies. I didn't see much advantage of using 130 nm, as I had to use quite long channel length to achieve an acceptable gain in ...

Question 12

Any resources that give in depth analysis of FinFET working would be helpful. I read a couple of papers on IEEE but most of them had very little information related to the working principle.

Question 13

I am researching the mode of operation on PMOS and NMOS using Level 1 standard parameters. This is the information of the NMOS circuit to be designed. Using transistor model level 1 parameters, ...

Question 14

I'm trying to draw a NMOS as shown above, but have some problems (the figure is from Razavi's book, the green box I added represents the N implant layer) In the process I used, there's a design rule ...

Question 15

This is probably a very broad question and I will try to be more specific. I'm asking this question to get a sense of the gap between my knowledge and a 'successful' tapeout, as I've heard many people ...

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Questions tagged [vlsi]

How to get graph abstraction from a .yal file [closed]

4-bit SAR ADC for my project

How would the MOSFTET M2 conduct in the given Differential Amplifier?

Two PMOS sharing the same NWELL

system verilog code error

What are the "rules" for counting transistors on a chip?

What would the critical path be for this circuit? [closed]

Why does this LC VCO work without varactor but becomes really noisy as soon as I add the varactors?

How to decide sizes for transistors in a design? What does it mean to design an IC?

Specific, practical examples of limits of logic gate fan-in?

How does analog IC benefit from channel length shrinking?

can someone explain the working /operation of FinFET?

Why simulation of single NMOS/PMOS on LTspice has big difference with manual calculation using Level 1 Standard Parameters?

A question about layout: How to connect the gate to metal 1 layer?

What is the standard procedure for analogue IC tapeout?

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