Verilog always block not clocking

Question

I have a 28Mhz clock which toggles a slowClk every 14 cycles:

always @( posedge clk28 ) begin if( ! notReset ) begin clkCount <= 0; end else begin if( clkCount >= 13 ) begin slowClk <= ~slowClk; clkCount <= 0; end else begin clkCount <= clkCount + 1; end end end

I can confirm that slowClk is toggling with Quartus SignalTap. Why is it that I cannot seem to use slowClk within another always/posedge block?

For example, I have a ClockDivider module:

module ClockDivider #(parameter DIVISOR) ( input clockIn, output clockOut ); bit[9:0] counter; always @(posedge clockIn ) begin counter <= counter + 1; if( counter >= (DIVISOR-1) ) begin counter <= 0; end clockOut <= (counter < DIVISOR / 2 ) ? 1'b1 : 1'b0; end endmodule

..but it refuses to give me an oscillating signal - it's as if clockIn is always high or low.

ClockDivider #(.DIVISOR(32)) clockDiv( .clockIn( slowClk ), .clockOut( clkOut ) );

Is it not possible to use posedge on a generated/toggled signal?

Check to see if you have any warnings from the synthesis tools (e.g. stuff being optimised away). Have a look at the post fit netlist to see if your divider logic is connected up. Check in simulation that the behaviour is as expected. — Tom Carpenter
– Tom Carpenter, Commented Jan 30 at 8:52

TonyM · Accepted Answer · 2025-06-21 11:09:28Z

"Is it not possible to use posedge on a generated/toggled signal?"

This is an X-Y question in terms of reliable digital design. It's not that you can't use a generated signal as a 'home-made' logic clock, it's that you shouldn't. Depending on the logic circuit, it can produce an unstable and unreliable design.

That's often tempting to do in an FPGA/CPLD: first putting clocks through and AND gate to produce a switched-off-able clock for control or to get low power; running a counter and taking the output of a flip-flop as a new CLKIN-divided-by-n clock. An example might be in making a communications controller (I2C, UART, SPI) by producing a clock near the bit frequency to operate the comms logic circuitry from.

The problem is it produces a new clock from gates (call it CLKG) that changes just after the original CLKIN does.

This is shown below, where after a CLKIN rise then (a) DFF3 inverts and inverts CLKG, (b) DFF1 output updates/changes. So DFF2 could see its CLK input rise just as its D input is changing and between logic voltages, not yet reaching a good HIGH or LOW logic level voltage. That would cause DFF2 to go metastable or to take the wrong level. This makes for an unstable and unreliable logic circuit.

It is possible to design gated clock circuits perfectly well, circuits that design out these problems or get round them. You'll see them routinely in ASICs. But the circuit is more complicated to design and maintain by others. The simplest and most reliable clock scheme is a single logic clock going from a PLL or input pin to all flip-flop clocks. The synthesis software will then require the least effort from you to produce a reliable circuit. Use more than one clock domain sparingly and because you absolutely have to.

You can then generate an enable signal that's asserted for 1 clock at the rate you need it. Design the slower logic, also running from the single global logic clock, to only advance when this enable is asserted. It's very straightforward to do and gives you a reliable, solid synthesised design that works across the device's voltage and temperature ranges.

Thanks @TonyM. Sorry I was away for a few days. It will take me a few days to get some spare time to get my head around this. I'm using a PLL to generate my 28MHz clock. I just want to divide the clock signal down to give me slower frequencies - as is done with the CBM Vic 20 audio channels. That has been working fine for 3 of the audio channels but I think I fed the clock dividers the 28MHz signal from the PLL. With the last channel, I fed in the signal produced by the toggle as shown in the description. — SparkyNZ
– SparkyNZ, Commented Feb 3 at 20:31
@SparkyNZ, no worries and I'm keen to help you with this. We can chat here — TonyM
– TonyM, Commented Feb 3 at 20:57
I couldn't send anything the in chat room but I'm keen to learn what you have to share. I also think I know what one of my problems is.. but I could really do with some help figuring out what I am seeing in the RTL Netlist view cf my Verilog module. — SparkyNZ
– SparkyNZ, Commented Feb 5 at 7:12

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